How a board is checked.

What runs between your requirements and the release, and what you get at the end. The pipeline at a glance →

One build, condensed.

Eight stages, each a script or a check. A failed gate stops the release and cannot be waived.

  1. Inputs
  2. Feasibility
  3. Schematic
  4. Board setup
  5. Placement
  6. Routing
  7. Checks
  8. Release
G1ERCwaitPASS
G2DRC + paritywaitPASS
G3Layout lintwaitPASS
G4RF lintwaitPASS
G5Second opinionwaitPASS
G6FootprintswaitPASS
G7SourcingwaitPASS
G8Thermal · S-param · SPICEwaitPASS
G9RenderswaitPASS

Representative session, condensed from the build chain of test run 10, the SpaceWire bridge.

A script does not read O as 0.

Net labels, pin tables, part numbers and datasheet values are compared exactly. Lookalike glyphs and misplaced decimals are caught.

#ReferenceAs drawnResult
01SD_DQ10SD_DQ1Ocol 7 · U+004F ≠ U+0030
02SPW_DIN_PSPW_DlN_Pcol 6 · U+006C ≠ U+0049
03LVDS_DOUT_NLVDS_DOUT_Nmatch
04SD_BA1SD_BAlcol 6 · U+006C ≠ U+0031
05SD_WE_NSD_VVE_Ncol 4 · V+V ≠ U+0057
06SPW_SOUT_PSPW_5OUT_Pcol 5 · U+0035 ≠ U+0053
07PROGRAMNPROGRAMNmatch
08R3 453k → 3.32 VR3 45.3k → 0.87 VVOUT off by 3.8×
  • PinsMCU pin maps against the datasheet tables
  • FootprintsLand patterns against supplier footprints
  • PartsMPN and order numbers against stock
  • NetsSchematic netlist against board copper

Every release knows its temperature.

A thermal model of the routed board. Junction temperatures and margins go into the design report.

Model output from the release package. Bench measurement of the first articles is the next milestone.

Field solverMicrostrip, CPWG, stripline and differential pairs on the real stackup.
S-parametersRF chains cascaded with gain, match, noise figure and stability.
SPICE benchesAnalog nodes simulated with datasheet limits as pass checks.
openEMS3D models of antennas and filters with Smith charts.

Every line sourced before the order.

Part numbers, order numbers and stock are checked; land patterns are compared with the supplier's footprints.

35
BOM lines, SpaceWire bridge
93
parts in the BOM
34 / 35
lines with LCSC numbers
CPL
rotations checked against LCSC

What you get.

One zip: a native KiCad project and everything a fab needs.

  • Opens in KiCad 10Native project files, nothing proprietary.
  • Imports into AltiumThrough Altium's KiCad importer; we check the import on request.
  • Yours to changeEdit it by hand, or send it back and the pipeline continues on the same project.
  • Any fabGerber, drill, BOM and placement in KiCad and JLCPCB formats.

Sample: test run 10 fab files and reports · zip, 2.9 MBIts KiCad files in the viewer →

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