Case study · test run 10Project card →
SpaceWire to SPI bridge.
Lattice MachXO2 FPGA, 32 MB SDRAM FIFO, LVDS SpaceWire PHY, 4 impedance-controlled layers. How the pipeline placed and routed it.
Layers4, JLC04161H-3313
Size78 × 66 mm
Parts93, both sides
ImpedanceSE 50.1 · LVDS 100.0 Ω
Thermal0.73 W · 34 °C
Gates9 / 9 pass
01 · RoutingRouting
Routed the way an engineer would.
- 01Placement from one geometry fileEvery coordinate, pin map and net order of the board lives in a single module.
- 02The SDRAM bus as a 45° fanThe memory bus leaves the FPGA as one disciplined bundle, not a tangle.
- 03Nested wraps around the memoryThe far row is carried around both ends of the package in parallel lanes.
- 04The router only for leftoversSlow nets go to the router under project rules; its result is frozen for reproducibility.
schematic · A2 · inverted
02 · SchematicGenerated
One sheet. Seven wired blocks.
The schematic is generated from the same geometry and pin maps as the layout, so the drawing and the copper cannot drift apart.
- 01Power input. USB-C 5 V, TVS, ferrite, TLV62569 buck to 3.3 V
- 02FPGA power. 100 nF at every VCC and VCCIO pin, 10 µF per bank
- 03Configuration. Internal flash, JTAG for the Lattice cable
- 04SDRAM FIFO. W9825G6KH, 32 MB at 100 MHz
- 05Host SPI. Slave to 80 MHz, IRQ, reset, Pmod 2A
- 06SpaceWire. SN65LVDS049, micro-D or lab header
- 07Clock and status. 25 MHz, reset, LEDs, debug header
03 · Stackup4 layers
Four layers. One intent.
- F.Cu · signalFPGA fan-out, SDRAM bus, LVDS pairs into the SpaceWire rows.
- In1.Cu · groundAn unbroken reference plane under every fast line.
- In2.Cu · 3.3 VThe supply plane, with fills under both packages.
- B.Cu · decouplingA 100 nF capacitor directly under every FPGA and SDRAM supply pin.
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